Voltage scaling has been used to reduce the power consumption of digital and analog circuits. It has been found that minimal energy may be achieved when the supply voltage is lowered below threshold voltage and the leakage energy balances the active energy.
However, aggressive reduction of the supply voltage may significantly degrade the performance as well as increase variations of circuits. Compared to deep sub-threshold operation, around-threshold or near-threshold operation has been considered to be more practical as energy reduction may be achieved at the same time with substantially improved performance as well as reduction in variation.
Future low power systems on chips (SOCs) are likely to include many components operating at around-threshold or near-threshold voltages to super-threshold voltages. This requires level shifters that are able to perform fast and energy efficient level shifting for a wide range of supply voltages from around-threshold or near-threshold voltages to super-threshold regions.
FIGS. 1A and 1B show schematics of two level shifters for super-threshold operations. FIG. 1A shows a schematic 100a of a level shifter based on the cross-coupled p-channel metal oxide field effect semiconductor (PMOS) transistors configuration. The level shifters include two n-channel metal oxide field effect semiconductor (NMOS) transistors 102, 104 and two p-channel metal oxide field effect semiconductor (PMOS) transistors 106, 108. The gate electrodes of the PMOS transistors 106, 108 are coupled to the drain electrode of the NMOS transistors 104, 102 respectively. An input voltage Vlow,in may be applied to node 110. Node 110 is coupled to the gate electrode of transistor 102. An input inverter 112 (power by voltage Vlow) is used to convert the input voltage to generate an inverted input voltage at the gate electrode of transistor 104. The drain electrodes of transistors 106, 108 are coupled to supply voltage VDD. An output inverter 114 may be used to electrically connect the drain electrode of transistor 102 to output node 116. When the voltage Vlow,in is applied to node 110, an output voltage about VDD may be generated at output node 116. Conversely, when a voltage of about 0 V is applied to node 110, an output voltage about 0V may be generated at output node 116.
This structure works well for input voltages well above threshold voltages. When the input voltage decreases to threshold levels, transistors 102 or 104 are nearly turned off. The pull down current is unable to overcome the pull up current and the level shifter may fail to flip. An intuitive solution is to increase the sizes of transistors 102 and 104. However, this is impractical because when the input voltages applied to transistors 102 or 104, transistors 102 and/or 104 conduct mainly sub-threshold currents which are several times smaller than the super-threshold currents flowing through transistors 106 and/or 108. For example, simulation shows that at 90 nm, transistors 102 and 104 have to be sized 2000 times larger than transistors 106 and 108 for the circuit to operate in the around-threshold region.
FIG. 1B shows a schematic 100b of a level shifter based on the current mirror configuration. The level shifter uses current-mirror to achieve level shifting. NMOS transistors 122, 124 and PMOS transistors 126, 128 are connected to form a current mirror. An input voltage may be applied at node 130. An input inverter 132 is used to generate an inverted input voltage from the input voltage. An output node 136 may be connected to the drain of transistor 124 to generate an output voltage. When the input voltage is high, there is current flowing through transistors 102, 106. An amplified current flows through transistors 104, 108 and charge the output node 136 to high (e.g. close to supply voltage VDD). When the input voltage is low, the current mirror is disabled and the output is discharged to low (e.g. close to ground). While the level shifter based on the current mirror configuration can operate at a lower supply voltage, there is a constant static current flowing through transistors 102, 106 when the output voltage is high, which results in a large standby leakage power consumption.
FIG. 2 shows a schematic 200 of a level shifter. The level shifter includes NMOS transistors 202, 204, 206, 208, 210, 212 and 214, PMOS transistors 216, 218, 220, 222, 224, 226, 228, 230, 232, 234 as well as inverted 238, 240. The level shifter includes a reduced swing inverter (RSI) 240 (including transistors 212, 214, 230, 232, 234) to achieve the pull-up path to achieve fast transition without heavily upsizing the pull down transistors. However, this structure uses more than 20 transistors which increase its area overhead and sensitiveness to process variation. Another drawback is that the propagation delay does not scale with voltage very well since the pull-up transistors are constantly weakened.
FIG. 3 shows a schematic 300 of a level shifter. The level shifter includes a first stage having NMOS transistors 302, 304 and PMOS transistors 306, 308. A diode connected PMOS transistor 310 acting as a load us used to weaken the pull-up path. The level shifter further includes a second stage cascaded with the first stage to achieve full swing of voltage. The second stage includes NMOS transistors 312, 314 and PMOS transistors 316, 318. The propagation of this level shifter does not scale very well with voltage especially when the supply voltage is raised above the threshold voltage since the drop across PMOS transistor 310 is nearly constant. As such, this level shifter may not be suitable for applications which require dynamic voltage scaling (DVS). Also, the level shifter may suffer from asymmetric rise and fall delay caused by the input inverter 320, especially at ultra low voltages due to the reduced conductance of the cross-coupled PMOS. During a fall transition (1→0), transistor 302 is switched off before transistor 304 is switched on due to the delay caused by the input inverter 320. The current flowing through transistors 302, 306 are close to zero. This causes reduced transconductance for switching and increases the fall delay. During a rise transition (0→1), the transistor 304 is switched off after the transistor 302 is switched on. The overlapped on-time leads to high conductance and small rise delay.
FIG. 4 shows a schematic 400 of a level shifter. The level shifter includes NMOS transistors 402, 404, 406, 408, PMOS transistors 410, 412, 414, 416, 418 as well as inverters 420, 422. The level shifter achieves fast level shifting by creating non-conflicting rise and fall transitions with feedback control. The disadvantage of this level shifter is the large size required for the pull-down transistors and increased active energy caused by the stacked transistor 406 in the pull-down path which is already weaker than the pull-up path. The asymmetry between the pull-up path and the pull-down path may also cause the circuit to lose its balance of rise and fall delay or even fail at lower voltages.
FIG. 5 shows a schematic 500 of a level shifter. The level shifter may include a inverter stage 502 and a modified current mirror level shifter stage 504. The inverter stage 502 may include a NMOS transistor 506 and a PMOS transistor 508. The modified current mirror level shifter stage 504 may include NMOS transistors 510, 512 as well as PMOS transistors 514, 516, 518. The NMOS transistors 510, 512 as well as PMOS transistors 514, 516, 518 form a Wilson current mirror. The level shifter uses feedback control (i.e. transistor 514) to disable the static current path through transistors 510, 516 to reduce the standby leakage current. However, disabling the static current path causes a voltage drop at the output when the output voltage is high due to the reduced mirror current. This creates another static current path in the subsequent buffer circuit and high standby leakage. Also, the transistor 518 is half activated (half ON) for low output which increases standby leakage power and fall delay. Increasing the size of transistor 518 may reduce the output voltage drop and reduce leakage current but may increase the standby leakage current for low output and increase the fall delay.
FIG. 6 shows a schematic 600 of a level shifter. The level shifter includes a level shifter stage including NMOS transistors 602, 604 and PMOS transistors 606, 608 arranged in the cross-coupled PMOS configuration. The level shifter further includes input inverters 610, 612. The level shifter further includes a substrate bias circuit 614 and a comparator 616 to apply forward body bias to the pull-down transistors 606, 608 for reducing propagation delays during transitions and apply reverse body-bias to reduce standby leakage out of transitions. However, this requires triple well technology and large area overhead caused by well separation, body bias-control and output detection. In addition, forward body-bias itself consumes leakage power.